The invention relates to a current divider for splitting up an input current into substantially equal output currents, comprising:
an input terminal for connecting the input current, PA1 first and second output terminals for tapping the output currents, PA1 current branches for coupling the input terminal and the output terminals to respective connecting terminals, PA1 switching means for coupling the connecting terminals in a switching cycle under the control of switching signals, PA1 current memory circuits inserted in at least one of the current branches, each circuit comprising first and second current terminals and a control terminal, for maintaining with a first control signal level on the control terminal a current flowing through the first and second current terminals during a second level of the control signal and PA1 a clock generator for generating the switching signals for the switching means and the control signals for the current memory circuits. PA1 the input terminal is coupled through a first and a second current branch to a first and a second connecting terminal respectively, the first current branch comprising a first variable current source for supplying a current which is the difference between the input current and a current flowing through the second current branch, and the second current branch comprising a first current memory circuit whose first current terminal is coupled to the input terminal and whose second current terminal is coupled to the second connecting terminal, PA1 the first and second output terminals are coupled through third and fourth current branches respectively, to third and fourth connecting terminals, the third current branch comprising a second current memory circuit whose first current terminal is coupled to the first output terminal and whose second current terminal is coupled to the third connecting terminal, PA1 the switching means are arranged for coupling during a first phase of the switching cycle the first to the third connecting terminal and the second to the fourth connecting terminal and for coupling during a second phase of the switching cycle the first to the fourth connecting terminal and the second to the third connecting terminal, and PA1 the clock generator is arranged for generating control signals which are coupled to respective control terminals of the first and second current memory circuits, the control signal for the control terminal of the first and the second current memory circuit respectively, assuming a value which corresponds to the first and the second level respectively, during at least part of the first phase of the switching cycle and corresponds to the second and the first level respectively, during at least part of the second phase of the switching cycle. PA1 a transistor having a control electrode and having first and second main electrodes coupled to the first and second current terminals respectively, the transistor of the first current memory circuit being of a first conductivity type and the transistor of the second current memory circuit being of a second conductivity type opposite to the first conductivity type, PA1 a hold-capacitor connected between the control electrode and the first main electrode and PA1 a switch between the control electrode and the second main electrode, which is open with the first level of the control signal and closed with the second level of the control signal,
A similar current divider is known from the article entitled "Very accurate current divider", Electronics Letters, 6 July 1989, Vol. 25, No. 14.
Current dividers are used, for example, in digital-to-analog converters in which a reference current is divided by means of a plurality of current dividers into a binary weighted series of currents which are connected to a junction point by means of switches in response to the bit values of a digital to be converted. With an augmenting number of bits ever more strict requirements are made on the accuracy of the current dividers. In static current dividers the attainable accuracy is restricted by tolerances in the manufacturing and design process of the components used.
The known current divider comprising CMOS transistors is of the dynamic type, in which the accuracy of the current division is substantially insensitive to the tolerances in the manufacturing and design process of the transistors used. The input current to be divided is distributed according to a cyclic switching pattern over a number of current branches comprising current memory circuits by means of the switching means controlled by switching signals. In dependence on the level of the control signals the current memory circuits operate as current consumer or current supplier, the supplied current being substantially equal to the previously consumed current. A clock generator supplies switch and control signals which are selected such that irrespective of the initial distribution of the current over the current branches, the currents through specific current branches converge to final values which are about half the input current. These currents form the output currents of the current divider.
A detrimental effect of the known current divider is that the output currents are available only during part of the cycle period of the switching pattern, which impedes the use of this divider in digital-to-analog converters which require continuously flowing currents.